RSP'08 Program

Presentation kit for authors.

Direct links to program information

• Symposium Program
• Symposium Tutorials
• Keynote speakers

The workshop will be held at the Hotel Casa Munras in Monterey, California, USA, in the Andalucia room.

Symposium Program

Tuesay the 3^rd of June

8.30 – 9.00: Registration

9.00 – 9:30: Introduction

• Message from the General Chairs

  • M. Shing - NPS, USA

  • W. Hardt - Tech. Univ. Chemnitz, Germany

• Message from the Program Chairs

  • F. Hessel - PUCRS, Br

  • J. Hugues - TELECOM ParisTech, F

9.30 – 10:30: Keynote Speech by Greg Bollella

• The RTSJ for Prototyping Real-Time Systems: A Case Study

10.30 – 10.50: Coffee Break

10.50 – 12.20 Session 1: System Specification, Session Chair: Fabiano Hessel, PUCRS, Brazil

• RealSpec: An Executable Specification Language for Prototyping Concurrent Systems
  A. Khwaja, J. Urban, Intel Corporation, USA
• Using MDE for the Rapid Prototyping of Space Critical Systems
  J. Hugues, M. Perrotin, T. Tsiodras, GET - Telecom Paris, France
• A Functional DIF for Rapid Prototyping
  W. Plishker, N. Sane, M. Kiemb, K. Anand, S. Bhattacharyya, University of Maryland, USA

12.20 – 13.40: Lunch

13.40 – 15.10 Session 2: Embedded Software Design, Session Chair: Klaus Müller-Glaser - Univ. Karlsruhe (ITIV), Germany

• High-Level Estimation of Execution Time and Energy Consumption for Fast Homogeneous MPSoCs Prototyping
  S. Filho , J. C. Palma , C. Marcon , F. Hessel, PUCRS, Brazil
• Software for Multi Processor System on Chip: moving from generic RISC platforms to CELL
  L. Demontes, M. Bonaciu, P. Amblard, University of Grenoble, France
• Multi-CPU/FPGA Platform Based Heterogeneous Multiprocessor prototyping: New Challenges for Embedded Software Designers
  B. Senouci , A. Kouadri-Mostéfaoui , F. Rousseau , F. Petrot, TIMA Laboratory, France

15.10 – 15.30: Coffee Break

15.30 – 17.00 Session 3: MPSoC Design, Session Chair: George Alexiou - Univ. Patras/RA-CTI, Greece

• Configurable Heterogeneous MPSoC Architecture Exploration Using Abstraction Levels
  H. Shen, P. Gerin, F. Petrot, TIMA Laboratory, France
• An Automated Design Flow for NoC-based MPSoCs on FPGA
  S. Lukovic, L. Fiorin, ALaRI-Faculty of Informatics-University of Lugano, Suisse
• Integrating Abstract NoC Models within MPSoC Design
  E. Moreno, K. Popovici, N. Calazans, A. Jerraya, PUCRS, Brazil and CEA-LETI, France

17.00 – 18.00 Industrial Panel Session: New Frontiers in Chip Design

• Moderator: F. Hessel (PUCRS, Brazil)
• Panelists: A. Donlin (Xilinx) [slides], F. Clermidy (CEA-LETI) [slides], G. Marin (Tensilica) [slides], A. Mathur (Calypto) [slides]

18.00 – 20.00 Welcome Reception

Wednesday, 4^th of June

9.00 – 10.00: Keynote Speech by Bruce Lewis

• Multi-Dimensional Model Based Engineering for Performance Critical Computer Systems Using AADL

10.00 – 10.30: Coffee Break

10.30 – 12.00 Session 4: Methodology, Session Chair: Jérôme Hugues - ENST Paris, France)

• Automation of Communication Refinement and Hardware Synthesis within a System-Level Design Methodology
  L. Moss, M. Cantin, G. Bois , M. Aboulhamid, École Polytechnique de Montréal and Université de Montréal, Canada
• A Methodology for Wireless Sensor Network Prototyping with Sophisticated Debugging Support
  H. Hinkelmann, A. Reinhardt, M. Glesner, Technische Universitaet Darmstadt, Germany
• Design Flow for Reconfiguration based on the Overlaying Concept
  A. Meisel, A. Draeger, S. Schneider, W. Hardt, Chemnitz University of Technology, Germany

12.00 – 13.30: Lunch

13.30 – 15.00: Session 5: Verification, Session Chair: Doron Drusinsky - Naval Postgraduate School, USA

• A Coverage-Driven Constraint Random-Based Functional Verification Method of Memory Controller
  Y. Wu, L. Yu, L. Lan, H. Zhou, Beijing Microelectronics Technology Institute, China
• Requirement Traceability in Software Developmet Process: An Empirical Approach
  S. Bhattacharya , S. Sengupta , A. Kanjilal, Jadavpur University, India
• Dynamic adaptation of Hardware-Software scheduling for Reconfigurable System-on-Chip
  F. Ghaffari, B. Miramond, F. Verdier, University of Cergy Pontoise, France

15.00 – 15.30: Coffee Break

15.30 – 17.30: Session 6: FPGA Design, Session Chair: Ahmed Jerraya - CEA-LETI, France

• A Multi-MicroBlaze Based SOC System: From SystemC Modeling to FPGA Prototyping
  S. Xu, H. Pollitt-Smith, CMC Microsystems, Canada
• From Application to ASIP-based FPGA prototype: a Case Study on Turbo Decoding
  O. Muller, A. Baghdadi, M. Jézéquel, TELECOM Bretagne, France
• A prototype of trusted platform functionality on reconfigurable hardware for bitstream updates
  B. Glas, A. Klimm, D. Schwab, K. Müller-Glaser, Jürgen Becker, University of Karlsruhe (ITIV), Germany
• Co-Design Architecture and Implementation for Point-Based Rendering on FPGAs
  M. Majer, S. Wildermann, J. Angermeier, S. Hanke, J. Teich, University Erlangen-Nuremberg, Germany

20.00: Banquet

Thursday, 5^th of June

9.00 – 10.00: Keynote Speech by Eric Sax

• Testing automotive system prototypes far before driving on the proving ground

10.00 – 10.30: Coffee Break

10.30 – 12.00 Session 7: Image Processing, Session Chair: Wolfram Hardt - TU Chemnitz, Germany

• Implementation Strategies for Statistical Codec Designs in H.264/AVC Standard
  X.H. Tian, T. M. Le, X. Jiang and Y. Lian, National University of Singapore, Singapore
• ASIP-controlled Integer Transform Codec for H.264/AVC Coding
  N.T. Ngo, T.T.T. Do, Y.S. Kadam, T.M. Le and A. Bermak (*), National University of Singapore, Singapore, (*) Hong Kong University of Science and Technology, Hong Kong
• A Novel System-on-Chip Architecture for Efficient Image Processing
  V. Mariatos, K. D. Adaos, G.P. Alexiou, Diaplous Machine Vision, Greece

12.00 – 13.30: Lunch

13.30 – 15.30 Session 8: Case Studies, Session Chair: Man-Tak Shing - Naval Postgraduate School, USA

• Application Specific Instruction Sets and their Impact on the Design Space Requirements of a Hardware Java Virtual Machine
  Ryan Wood , Joseph Libby , Kenneth Kent, University of New Brunswick, Canada
• Flexible Software-Hardware Network Intrusion Detection System
  Kenneth Kent , Eric Aubanel , Ryan Proudfoot , Nan Chen, University of New Brunswick, Canada
• MAJIC: Multi-Agent Java Interface Controller
  Greg Ball, Naval Postgraduate School, USA
• Bandwidth Requirement Determination for a Digitally Controlled Cavity Synchronisation in a Heavy Ion Synchrotron Using Ptolemy II
  Christopher Spies , Peter Zipf , Manfred Glesner , Harald Klingbeil, Technische Universität Darmstadt, Germany

15.30 – 16.00

• Information about RSP’09
• Farewell

Tutorials Program

T1, June 2^nd 2008, 9am-12am: Fabien Clermidy "Network-on-Chip (NoC) theory and practice: General concepts, state-of-the-art and applications."

To solve the limitations of bus-based SoC designs in terms of bandwidth as well as complexity management, we need new interconnect structures, called Network-on-Chip. NoC concept proposes scalable communications with high bandwidth. It aims at simplifying the design thanks to a unified approach of communications, allowing technology-dispersion tolerant and power efficient structures. However, NoC based design needs to overcome difficulties such as application mapping on a massively parallel structure.

The tutorial introduces the NoC concepts and reviews the state-of-the-art of this research field. It also shows an applicative NoC implementation to underline the concepts. The attendees will learn the benefits to use a NoC in their design, the way to do it, and will have some elements to understand the application mapping issue.

Fabien Clermidy held a Master degree in 1994 and a Ph.D in engineering science in 1999. After being the NoC architect in a previous project, he is currently the project leader of a SoC for telecommunication in Grenoble. This development is the third NoC platform designed in the Grenoble CEA-LETIâs team. F. Clermidy is the writer or co-writer of 7 patents in the NoC field.

T2, June 2^nd 2008, 2pm-5pm: Doron Drusinsky "Light-Weight UML-based Formal Validation and Verification Methodology and Tool"

This tutorial will present a methodology and tool for light-weight UML-based validation and verification (V&V) of reactive systems, as currently used by NASA's V&V center. Topics to be covered are:

• The dimensions of V&V
• Light-weight vs. heavy-weight V&V
• Assertions as requirement representatives.
• The StateRover tool introduction, using the Eclipse plug-in.
• UML-based formal specification of reactive system properties:
  • UML Statecharts overview
  • Deterministic statechart assertions
  • Non-deterministic statechart assertions
  • A taste of power user specifications: quantification, past-time requirements.
• Exercising validation with the StateRover
• Using animation for visual debugging
• Verification: execution based model checking

Doron Drusinsky, B.Sc. 1983, Technion, Haifa, Israel, Ph.D. 1988, Weizmann Inst., Israel., Gad Reshef award. From 1988-1992 Doron worked for Sony corp., where he developed one of the first hardware synthesis tools and participated in one of the first commercial digital cell phone voice compression project. In 1993, Doron established R-Active Concepts, Inc., a provider of high-level development tools for embedded systems market; in this capacity Doron invented the first efficient code generator for Harel statecharts. These tools were acquired by ISI, now part of Wind River Systems, in 1997. In 1998 Doron established Time-Rover Inc., and developed the Temporal Rover and DBRover, the first run-time verification tools, which were used by NASA JPL for the verification of the Deep Impact fault detection module. Doron later authored the StateRover UML modeling, run-time verification, and execution based model checking tool currently in active production use by the Missile Defense National Team and NASA. He published a book on these subjects in 2006. From 2000 to 2002 Doron participated in the development of wide area low cost sensor systems at Xerox PARC. Doron joined NPS in 2002.

Keynote speakers

Greg Bollella, June 3^rd 2008

• Title: "The RTSJ for Prototyping Real-Time Systems: A Case Study"

• BIO: Dr. Greg Bollella, Distinguished Engineer and Director of Strategy for Real-Time Java at Sun Microsystems, has been interested in algorithms and software architectures that support the deterministic execution of logic within general-purpose operating systems and virtual machines since 1992. While a Senior Architect at IBM, he was fundamental to the industry effort which led to the creation of the Java Community Process and established JSR-01, the first activity under the JCP. Greg led the JSR-01 Expert Group which defined the Real-Time Specification for Java. During his work on the Golden Gate project at Sun he concurrently held a position, for four years, at the Jet Propulsion Laboratory, California Institute of Technology, as Distinguished Visiting Scientist. Within the Software organization at Sun, Greg leads the engineering effort of the 'Sun Java Real- Time System', a product implementation of JSR-01, leads the definition of Sun's real-time Java strategy, recently started the BlueWonder project which will produce the first Sun system, based on Solaris 10 and Java RTS, for industrial control, and works closely with customers on software architectures and systems design utilizing the features and capabilities of Java RTS. Greg holds a Ph.D. in computer science from the University of North Carolina at Chapel Hill. His dissertation research is in real-time scheduling theory and real-time systems implementation and outlines an architecture and defines fundamental issues for supporting real-time applications within general- purpose operating systems and language runtimes.

Bruce Lewis, June 4^th 2008

• Title: "Multi-Dimensional Model Based Engineering for Performance Critical Computer Systems Using AADL" [slides]

• BIO: Bruce Lewis is a senior experimental developer for the US Army's Aviation and Missile Command, Research, Development and Engineering Laboratory, Software Engineering Directorate (SED). His research has focused on embedded computer system architecture, reuse, and system evolution since 1991. He has served as the government lead on various DARPA projects related to ADLs and real-time systems, including those developing the MetaH Architecture Description Language. He is the chairman of the Society of Automotive Engineers, Avionic Systems, Architecture Design Language Committee, AS-2C, and led the standardization of the Architecture Design and Analysis Language, AS5506 and AS5506/1.

Eric Sax, June 5^th 2008

• Title: "Testing automotive system prototypes far before driving on the proving ground"

• Dr.-Ing. Eric Sax studied electronics engineering at the University of Karlsruhe, Germany. Thereafter he worked as a computer scientist at the Forschungszentrum Informatik (FZI). He received the Dr.-degree in 2000. His thesis was about "mixed-signal testing". Since 2002 he is with MBtech and runs there now the division "EE Test-Engineering".

Note: the program of previous editions are available under the "history" section.