RSP'10 Program

Direct links to program information

• Symposium Program
• Symposium Tutorials
• Keynote speakers

Note there will be a refreshment banquet on Tuesday, 8th after the tutorials

Symposium Program

Wednesday the 9^th of June

8.00 – 8.30: Registration

8.30 – 8:45: Introduction

• Message from the General Chairs

  • G. Nicolescu - Polytechnique Montreal, Canada

• Message from the Program Chairs

  • P. Athanas - Virginia Tech, USA

  • J. Hugues - ISAE, France

8:45 – 9:45: Keynote Speech by Jose Munoz

9.45 – 10.00: Coffee Break

10.00 – 12.00 Session 1: Applications, Session Chair: Fabiano Hessel

• Fabrizio Ferrandi and Marco Lattuada
  Fine Grain Analysis of Simulators Accuracy for Calibrating Performance Models
• Zulfiqar Ali, Ali Arshad and Umair Razzaq
  An FPGA based semi-parallel architecture for higher order Moving Target Indication (MTI) processing
• Ronaldo Husemann, Mariano Majolo, Roesler Valter, JosÂŽ Valdeni Lima and Altamiro Susin
  High Efficient Forward Two-Dimensional DCT Module Architecture for H.264/SVC
• Trang T. T. Do, Thinh M. Le, Binh P. Nguyen and Yajun Ha
  Performance-Cost Analyses Software for H.264 Forward/Inverse Integer Transform

12.00 – 13.30: Lunch

13.30 – 15.30 Session 2: Tools and methods, Session Chair: Jerome Hugues

• Doron Drusinsky and Man-Tak Shing
  Validating Quality Attribute Requirements via Execution-based Model Checking
• Hsiang-Huang Wu, Hojin Kee, Nimish Sane, William Plishker and Shuvra Bhattacharyya
  Rapid Prototyping for Digital Signal Processing Systems using Parameterized Synchronous Dataflow Graphs
• Martin Hillenbrand, Matthias Heinz and Klaus D. Mueller-Glaser
  Failure mode and effect analysis based on electric and electronic architectures of vehicles to support the safety lifecycle ISO/DIS 26262
• Martin Hillenbrand, Matthias Heinz and Klaus D. Mueller-Glaser
  Rapid specification of hardware-in-the-loop test systems in the automotive domain based on the electric/electronic architecture description of vehicles

15.30 – 16.00: Coffee Break

16.00 – 17.30 Session 3: Network-on-Chip, Session Chair: Peter Athanas

• Walid Lafi, Didier Lattard and Ahmed Jerraya
  An efficient hierarchical router for 3D NoC architecture
• Atef Allam, Ian O'Connor and Wim Heirman
  Performance Evaluation for Passive-Type Optical Network-on-Chip
• Philipp Mahr and Christophe Bobda
  Reconfigurable Router for Dynamic Networks-on-Chip

Thursday the 10^th of June

8:45 – 9:45: Keynote Speech by Luca Benini

9.45 – 10.00: Coffee Break

10.00 – 12.00 Session 4: Model-Based Development, Session Chair: Man-Tak Shing

• Julien Delange, Laurent Pautet and Fabrice Kordon
  Design, Verification and Implementation of MILS systems
• Ananya Kanjilal, Sabnam Sengupta and Swapan Bhattacharya
  Scenario Path Identification in Distributed Environment: A Model Based Approach
• Graham Hemingway, Joseph Porter, Nicholas Kottenstette, Harmon Nine, Chris vanBuskirk, Gabor Karsai and Janos Sztipanovits
  Automated Synthesis of Time-Triggered Architecture-based TrueTime Models for Platform Effects Simulation and Analysis
• Andrew Forward, Omar Badreddin and Timothy C. Lethbridge
  Towards Combining Model Driven with Prototype Driven System Development

12.00 – 13.30: Lunch

13.30 – 15.30 Session 5: Special session on Rapid Prototyping, Session Chair: Giovanni Beltrame

• Samar Abdi, Yonghyun Hwang, Lochi Yu, Hansu Cho, Ines Viskic, Daniel D. Gajski Embedded System Environment
• Gunar Schirner Exploring SW Performance Using Preemptive RTOS Models
• Andreas Gerstlauer Host-Compiled Simulation of Multi-Core Platforms
• William Plishker, Chung-Ching Shen, Shuvra S. Bhattacharyya, George Zaki, Soujanya Kedilaya, Nimish Sane, Kishan Sudusinghe, Tony Gregerson, Jie Liu, Michael Schulte Model-based DSP Implementation on FPGAs

15.30 – 16.00: Coffee Break

16.00 – 17.30 Session 6: Multicore systems, Session Chair: Gabriela Nicolescu

• Bruno Girodias, Luiza Gheorghe, Youcef Bouchebaba, Gabriela Nicolescu, El Mostapha Aboulhamid, Michel Langevin and Pierre Paulin
  Combining Memory Optimization with Mapping of Multimedia Applications for Multi-Processors System-on-Chip
• youcef bouchebaba, Gabriela Nicolescu and Pierre Paulin
  MpAssign: A Framework for Solving the Many-Core Platform Mapping Problem
• Gavin Xiaoxu Yao, Ray C.C. Cheung and Kim Fung Man
  Counter Embedded Memory Architecture for Trusted Computing Platform

18.00 – 20.00: Conference Banquet

Friday the 11^th of June

8:45 – 9:45: Keynote Speech by Janos Sztipanovits

9.45 – 10.00: Coffee Break

10.00 – 12.00 Session 7: Embedded Systems, Session Chair: Klaus Mueller-Glaser

• Alexandra Aguiar and Fabiano Hessel
  Embedded Systems' Virtualization: The Next Challenge?
• Weiqin Ma, Jyh-Charn Liu and Alessandro Forin
  Rapid Prototyping and Compact Testing of CPU Emulators
• Adolfo Recio, Jorge Suris and Peter Athanas
  Automatic Modulation Classification for Rapid Radio Deployment
• Martin Hillenbrand, Matthias Heinz, Nico Adler, Klaus D. Müller-Glaser, Johannes Matheis, Clemens Reichmann
  An Approach for Rapidly Adapting the Demands of ISO/DIS 26262 to Electric/Electronic Architecture Modeling

Tutorials Program

Tutorials are scheduled June, 8th, 2010.

Tutorial #1: Multi-core architectures design space analysis for embedded systems

• Local information: June, 8th, 9 am - 12 pm

• Abstract: Due to the complexity increase of embedded applications, multi-core systems on chip (MPSOC) are becoming the mainstream for architecture design. Indeed, according to ITRS, the number of cores in high-end systems will exceed 100 cores in 2012. With an expected 32% a year increase in the number of cores per die, the concept of multi-cores will even evolve to many-cores in the coming years. The Design space of such architectures is huge, and it is difficult for an embedded system designer to qualify the pros and cons of each approach. It is also very challenging to evaluate the programming model friendliness or the ability of the architecture to fulfill performance, power or reliability constraints. In this context, this talk aims at paving the design space of multi- and many-cores architectures with examples coming from state of the art devices. By analyzing associated execution models and their implementations, the objective is to give to the audience the ability to distinguish application domains that fits to each class of MPSOC architectures.

• About the Speaker Raphael David is in charge of the Multi-core architectures design team at the CEA LIST. He received his Ph.D. degree in computer engineering for having designed the DART reconfigurable processor, from the University of Rennes I, France, in 2003. He has joined the CEA LIST in a post-doctoral position to study reconfigurable architectures benefits to reduce power consumption of embedded systems. Since 2004 he has proposed dynamic execution models for programmable and reconfigurable multi- and many-cores systems to support variable execution conditions, either coming from technology or data-dependant applications. He is now in charge of the MPSOC design team in the Embedded Computing Lab of the CEA LIST and explores the architectures design space to support such advanced execution models. He is also involved in the implementation of dynamically reconfigurable processors for image processing and low power design.

Tutorial #2: A Turnkey Solution for Real-Time Rapid Prototyping and Hardware-In-The-Loop Simulation Using Simulink

• Local information: June, 8th, 2 pm - 5 pm

• Abstract: This tutorial will provide an overview of a real-time rapid prototyping and hardware-in-the-loop simulation solution from The MathWorksTM. Simulink is an environment for multidomain simulation and Model-Based Design of dynamic and embedded systems. xPC TargetTM is a high-performance, host- target platform that enables you to connect your Simulink models to physical systems for real time operations. In this tutorial we will cover modeling and simulation with Simulink, configuring models to execute in real time using xPC Target, and communicating with hardware devices to see Simulink models and algorithms in action. Application-based tutorials for control systems, state logic, and signal processing will be demonstrated.

• About the speaker Doug Jones is a Product Engineer at the MathWorks where he is involved in the development of rapid prototyping and hardware-in-the-loop simulation technologies. Prior to joining the MathWorks in 2006, he worked as an Electronics Engineer for the U.S. Air Force at Eglin Air Force Base, FL in both the 46th Test Wing's Guided Weapons Evaluation Facility and the Air Force Research Laboratory's Munitions Directorate.

Keynote speakers

Janos Sztipanovits Director of Institute for Software Integrated Systems, University of Vanderbilt, USA.

• Title: "The System Integration Challenge: Is Rapid System Prototyping Relevant to the Solution?"

• Abstract: System integration is the elephant in the room of large-scale system design. It would be hard to find any other technology that is more undervalued scientifically and at the same time has bigger impact on the presence and future of engineered systems. System integration is hard because this is the phase where essential design concerns – usually separated into software, systems and control engineering – are coming together and the hidden, poorly understood interactions and conflicts surface. Our current technology cannot provide sufficient predictability for partially compositional properties, which is a common situation in all large scale system development. The emerging technology of model-based engineering has the potential to make real change here. The talk describes experience and conclusions with model-based, rapid system prototyping applied in large-scale software-intensive system projects to explore and evaluate architectural designs before the systems are actually implemented.

• Bio: Dr. Janos Sztipanovits is currently the E. Bronson Ingram Distinguished Professor of Engineering and professor of Electrical Engineering, Computer Science and Computer Engineering at Vanderbilt University. He is founding director of the Institute for Software Integrated Systems (ISIS) at Vanderbilt University. Between 1999 and 2002, he worked as program manager and acting deputy director of DARPA Information Technology Office. Currently, he is member of the US Air Force Science Advisory Board. His research areas are at the intersection of systems and computer science and engineering. His current research interest is the foundation and applications of Model-Integrated Computing, an emerging model-based design technology for distributed embedded software, which is used in a wide range of defense and commercial systems. His other research contributions include structurally adaptive systems, autonomous systems, design space exploration and systems-security co-design technology. He has co-authored two books and over 250 papers.

Dr. Jose L. Munoz Deputy Director, National Science Foundation (NSF) Office of Cyberinfrastructure (OCI) and NSF/ICI senior science advisor, USA.

• Title:Reconfigurablye Computing and Rapid Systems Prototyping: An Oxymoron?

• Abstract: As we build every increasingly complex systems the demand for rapid systems prototyping has been moving from "it'd be nice if..." to "we cannot afford to not..". Driven by issues such as safety, costs, time-to-market timing it is imperative that system designers have at their fingertips the necessary tools and techniques to go far beyond back of the envelop analysis to breadboard/brassboard experimental units that would enable the developers to gain the critical insights necessary before further commitment of funds and/or resources.

  In a very real sense these are resources that can be used to predict the viability of particular approaches and could therefore to used to form a basis for a more informed decision. It is therefore necessary that “error bars� be placed on data collected so that different approaches could more readily be compared and contrasted. What role can/should reconfigurable computing play in rapid systems prototyping? Should its role end at the prototyping stage or should it be considered as the end-product? This are some of the questions/issues that will be presented... with perhaps more questions than answers.

Luca Benini, Universita di Bologna & STMicroelectronics.

• Title: "P2012: A many-core platform for 10Gops/mm2 multimedia computing"

• Abstract: Programmability is a key requirement for fast time-to-market and agile adaptation to rapidly evolving multimedia standards and customer expectations. Unfortunately, programmable architectures come with order-of-magnitude computational density and energy efficiency gaps with respect to custom-fit hardware. Is there a way to escape the flexibility vs. efficiency dualism? Is nano-scale silicon technology adding new facets to this "no free lunch" view? In this talk I will describe the architectural foundations of STMicroelectronics Platform 2012 project and provide some insight on how we hope to give positive answers to these fundamental questions.

• Bio: Luca Benini is Full Professor at the Department of Electrical Engineering and Computer Science (DEIS) of the University of Bologna and a Visiting Professor at the Ecole Polytechnique Federale de Lausanne (EPFL). He currently serves as Chief Architect for the Platform 2012 project in STMicroelectronics. Dr. Benini's research interests are in the design of system-on-chip platforms for embedded applications. He is also active in the area of energy-efficient smart sensors and sensor networks for biomedical and ambient intelligence applications. He has published more than 500 papers in peer-reviewed international journals and conferences, four books and several book chapters. He is a Fellow of the IEEE and a member of the steering board of the ARTEMISIA European Association on Advanced Research & Technology for Embedded Intelligence and Systems.